Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Using Design Space Exploration for Finding Schedules with Guaranteed Reaction Times of Synchronous Programs on Multi-core Architecture (2017) Li Z, Park H, Malik A, Wang KIK, Salcic Z, Kuzmin B, Glaß M, Teich J Journal article Formal Timing Analysis of Non-Scheduled Traffic in Automotive Scheduled TSN Networks (2017) Smirnov F, Glaß M, Reimann F, Teich J Conference contribution Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores (2017) Aliee H, Banaiyianmofrad A, Glaß M, Teich J, Dutt N Conference contribution Application Mapping Methodologies for Invasive NoC-Based Architectures (2017) Weichslgartner A Thesis High Performance Network-on-Chip Simulation by Interval-based Timing Predictions (2017) Roloff S, Hannig F, Teich J Conference contribution, Conference Contribution Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning (2017) Schmidt B, Ziener D, Teich J, Zöllner C Journal article Symbolic Parallelization of Nested Loop Programs (2017) Tanase AP Thesis Convoy Tracking for ADAS on Embedded GPUs (2017) Fickenscher J, Reinhart S, Bouzouraa ME, Hannig F, Teich J Conference contribution TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays (2017) Sousa É, Chakraborty A, Tanase AP, Hannig F, Teich J Conference contribution, Abstract of a poster A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays (2017) Sousa É, Tanase AP, Hannig F, Teich J Conference contribution