Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Auto-vectorization for Image Processing DSLs (2017) Reiche O, Kobylko C, Hannig F, Teich J Conference contribution, Conference Contribution Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors (2017) Brand M, Hannig F, Tanase AP, Teich J Conference contribution, Original article High Performance Network-on-Chip Simulation by Interval-based Timing Predictions (2017) Roloff S, Hannig F, Teich J Conference contribution, Conference Contribution TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays (2017) Sousa É, Chakraborty A, Tanase AP, Hannig F, Teich J Conference contribution, Abstract of a poster Efficient Task Spawning for Shared Memory and Message Passing in Many-core Architectures (2017) Zaib A, Heisswolf J, Weichslgartner A, Wild T, Teich J, Becker J, Herkersdorf A Journal article ActorX10: An Actor Library for X10 (2016) Roloff S, Pöppl A, Schwarzer T, Wildermann S, Baader M, Glaß M, Hannig F, Teich J Conference contribution Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays (2016) Witterauf M, Tanase AP, Hannig F, Teich J Conference contribution RamCrypt: Kernel-based Address Space Encryption for User-mode Processes (2016) Götzfried J, Müller T, Drescher G, Nürnberger S, Backes M Conference contribution, Conference Contribution Exzess: Hardware-based RAM encryption against physical memory disclosure (2016) Würstlein A, Gernoth M, Götzfried J, Müller T Conference contribution, Conference Contribution Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs (2016) Weichslgartner A, Wildermann S, Götzfried J, Freiling F, Glaß M, Teich J Conference contribution, Conference Contribution