Professur für Höchstleistungsrechnen

Complexities of Performance Prediction for Bandwidth-Limited Loop Kernels on Multi-Core Architectures (2010) Eitzinger J, Hager G, Wellein G Conference contribution Leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters (2010) Wittmann M, Hager G, Eitzinger J, Wellein G Journal article A Flexible Patch-Based Lattice Boltzmann Parallelization Approach for Heterogeneous GPU-CPU Clusters (2010) Feichtinger C, Habich J, Köstler H, Hager G, Rüde U, Wellein G Other publication type Efficient temporal blocking for stencil computations by multicore-aware wavefront parallelization (2009) Wellein G, Hager G, Zeiser T, Wittmann M, Fehske H Conference contribution Speeding up a Lattice Boltzmann Kernel on nVIDIA GPUs (2009) Habich J, Zeiser T, Hager G, Wellein G Conference contribution Vector Computers in a World of Commodity Clusters, Massively Parallel Systems and Many-Core Many-Threaded CPUs: Recent Experience Based on an Advanced Lattice Boltzmann Flow Solver (2009) Zeiser T, Hager G, Wellein G Book chapter / Article in edited volumes RZBENCH: performance evaluation of current HPC architectures using low-level and application benchmarks (2009) Hager G, Stengel H, Zeiser T, Wellein G Book chapter / Article in edited volumes The world's fastest CPU and SMP node: Some performance results from the NEC SX-9 (2009) Zeiser T, Hager G, Wellein G Conference contribution Challenges and Potentials of Emerging Multicore Architectures (2009) Stürmer M, Wellein G, Hager G, Köstler H, Rüde U Conference contribution Benchmark analysis and application results for lattice Boltzmann simulations on NEC SX vector and Intel Nehalem systems (2009) Zeiser T, Hager G, Wellein G Journal article