Prof. Dr.-Ing. Dietmar Fey

Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Generation of Executable Runtime Constrained Random Programs Functional Processor Verification (2016) Bauer W, Kohl J, Bäsig J, Rübesam S, Fey D Conference contribution Embedded Parallel Computing Accelerators for Smart Control Units of Frequency Converters (2016) Vaas S, Reichenbach M, Hofmann J, Stadelmayer T, Fey D Conference contribution A SystemC Based Framework for Cycle Accurate Processor Simulation and Parameter Analysis (2016) Kohl J, Demel C, Reichenbach M, Fey D Conference contribution Dataflow Optimization for Programmable Embedded Image Preprocessing Accelerators (2016) Lieske T, Reichenbach M, Ringlein B, Fey D Conference contribution, Conference Contribution Cache Aware Instruction Accurate Simulation of a 3-D Coastal Ocean Model on Low Power Hardware (2016) Schönwetter D, Ditter A, Aizinger V, Reuter B, Fey D Conference contribution Hardware-Software Co-Simulation of Self-Organizing Smart Home Networks: Who am I and where are the others? (2016) Kleinert B, Schäfer F, Weiß S, Bakakeu Ngassam RJ, Fey D Conference contribution Adaptive Synchronization Interface for Hardware-Software Co-Simulation based on SystemC and QEMU (2016) Kleinert B, Weiß S, Schäfer F, Bakakeu Ngassam RJ, Fey D Conference contribution Investigation of Strategies for an Increasing Population Size in Multi-objective CMA-ES (2016) Limmer S, Fey D Conference contribution Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits (2016) Fey D, Reichenbach M, Söll C, Biglari M, Röber J, Weigel R Conference contribution, Original article Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks (2016) Häublein K, Hartmann C, Reichenbach M, Fey D Conference contribution