Prof. Dr.-Ing. Dietmar Fey

Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations (2021) Fritscher M, Knödtel J, Reiser D, Mallah M, Pechmann S, Fey D, Reichenbach M Conference contribution, Original article Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design (2021) Vaas S, Ulbrich P, Eichler C, Wägemann P, Reichenbach M, Fey D Conference contribution, Conference Contribution Programming Reconfigurable Heterogeneous Computing Clusters Using MPI with Transpilation (2020) Ringlein B, Abel F, Ditter A, Weiss B, Hagleitner C, Fey D Conference contribution A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories (2020) Knödtel J, Fritscher M, Reiser D, Fey D, Breiling M, Reichenbach M Conference contribution, Conference Contribution Direct state transfer in MLC based memristive ReRAM devices for ternary computing (2020) Fey D, Reuben JR Conference contribution Impact of Performance Estimation on Fast Processor Simulators (2020) Rachuj S, Fey D, Reichenbach M Conference contribution, Conference Contribution Disjoint Sum of Products by Orthogonalizing Difference-Building circle minus (2020) Can Y, Yaz O, Fey D Journal article ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters (2020) Ringlein B, Abel F, Ditter A, Weiss B, Hagleitner C, Fey D Conference contribution Bridging the architecture gap: Abstracting performance-relevant properties of modern server processors (2020) Hofmann J, Alappat C, Hager G, Fey D, Wellein G Journal article TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities (2020) Hosseinzadeh S, Biglari M, Fey D Conference contribution, Original article