Mehrdad Biglari

Lehrstuhl für Informatik 3 (Rechnerarchitektur)

TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms (2021) Hosseinzadeh S, Biglari M, Fey D Journal article TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities (2020) Hosseinzadeh S, Biglari M, Fey D Conference contribution, Original article Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford-PKU Model (2020) Reuben JR, Biglari M, Fey D Journal article Reducing Hibernation Energy and Degradation in Bipolar ReRAM-Based Non-Volatile Processors (2019) Biglari M, Lieske T, Fey D Journal article High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States (2018) Biglari M, Lieske T, Fey D Conference contribution, Original article Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs (2018) Lieske T, Biglari M, Fey D Conference contribution, Original article A Non-Volatile Flip-Flop Using Memristive Voltage Divider (2017) Biglari M, Fey D Conference contribution, Abstract of a poster Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment (2017) Wust D, Biglari M, Knödtel J, Reichenbach M, Söll C, Fey D Conference contribution, Original article Memristive Voltage Divider: A Bipolar ReRAM-based Unit for Non-Volatile Flip-Flops (2017) Biglari M, Fey D Conference contribution, Original article Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits (2016) Fey D, Reichenbach M, Söll C, Biglari M, Röber J, Weigel R Conference contribution, Original article