Prof. Dr. Gerhard Wellein

Professur für Höchstleistungsrechnen

RZBENCH: performance evaluation of current HPC architectures using low-level and application benchmarks (2009) Hager G, Stengel H, Zeiser T, Wellein G Book chapter / Article in edited volumes The world's fastest CPU and SMP node: Some performance results from the NEC SX-9 (2009) Zeiser T, Hager G, Wellein G Conference contribution Challenges and Potentials of Emerging Multicore Architectures (2009) Stürmer M, Wellein G, Hager G, Köstler H, Rüde U Conference contribution Benchmark analysis and application results for lattice Boltzmann simulations on NEC SX vector and Intel Nehalem systems (2009) Zeiser T, Hager G, Wellein G Journal article Selecting an Appropriate Computational Platform for Supporting the Development of New Catalyst Carriers (2009) Zeiser T, Hager G, Wellein G, Inayat A, Schwieger W, Heidig T, Freund H Journal article, Original article Direct numerical simulation of turbulent flow over dimples - Code optimization for NEC SX-8 plus flow results (2008) Breuer M, Zeiser T, Hager G, Wellein G, Lammers P Book chapter / Article in edited volumes Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers (2008) Hager G, Zeiser T, Wellein G Conference contribution Data access characteristics and optimizations for SUN ULTRASPARC T2 AND T2+ systems (2008) Hager G, Zeiser T, Wellein G Journal article What's next? Evaluating Performance and Programming Approaches for Emerging Computer Technologies (2008) Wellein G, Hager G, Rüde U Other publication type Performance comparison of different parallel lattice Boltzmann implementations on multi-core multi-socket systems (2008) Donath S, Iglberger K, Wellein G, Zeiser T, Nitsure A, Rüde U Journal article