Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019 (2019) Teich J, Fummi F Edited Volume Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and its Application to Cellular Modems (2019) Ah Sue J, Brand P, Falk J, Hasholzner R, Teich J Conference contribution, Conference Contribution Performance Comparison between Machine Learning based LTE Downlink Grant Predictors (2019) Nisar A, Ah Sue J, Teich J Conference contribution Synthesizing High-Performance Image Processing Applications with Hipacc (2019) Özkan MA, Reiche O, Qiao B, Membarth R, Teich J, Hannig F Conference contribution, Conference Contribution Variety-Aware Routing Encoding for Efficient Design Space Exploration of Automotive Communication Networks (2019) Smirnov F, Pourmohseni B, Glaß M, Teich J Conference contribution, Original article Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic (2019) Brand M, Witterauf M, Hannig F, Teich J Conference contribution, Original article Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures (2019) Aliee H, Khosravi F, Teich J Conference contribution ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing (2019) Becher A, Herrmann A, Wildermann S, Teich J Conference contribution, Conference Contribution Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks (2018) Smirnov F, Reimann F, Teich J, Glaß M Journal article, Original article Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution (2018) Schmitt C, Schmid M, Kuckuk S, Köstler H, Teich J, Hannig F Journal article, Original article