Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures (2016) Häublein K, Reichenbach M, Reiche O, Özkan MA, Fey D, Hannig F, Teich J Conference contribution LoopInvader: A Compiler for Tightly Coupled Processor Arrays (2016) Tanase AP, Witterauf M, Sousa É, Lari V, Hannig F, Teich J Conference contribution Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016 (2016) Fanucci L, Teich J Book chapter / Article in edited volumes Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays (2016) Witterauf M, Tanase AP, Hannig F, Teich J Conference contribution Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design (2016) Wang B, Xu Y, Hasholzner R, Drewes C, Rosales R, Graf S, Falk J, et al. Conference contribution Invasive Computing for Timing-Predictable Stream Processing on MPSoCs (2016) Wildermann S, Bader M, Bauer L, Damschen M, Gabriel D, Gerndt M, Glaß M, et al. Journal article Recap of the 2016 DATE Conference & Exhibition (2016) Fanucci L, Teich J Journal article Architecture of computing systems – ARCS 2016: 29th international conference Nuremberg, Germany, April 4-7, 2016 Proceedings (2016) Hannig F, Cardoso J, Fey D, Schröder-Preikschat W, Teich J Authored book, Volume of book series Guiding Genetic Algorithms Using Importance Measures for Reliable Design of Embedded Systems (2016) Aliee H, Vitzethum S, Glaß M, Teich J, Borgonovo E Conference contribution HIPAcc: A Domain-Specific Language and Compiler for Image Processing (2016) Membarth R, Reiche O, Hannig F, Teich J, Körner M, Eckert W Journal article