Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

ABACUS: ASIP-based Avro Schema-customizable Parser Acceleration on FPGAs (2024) Hahn T, Schüll D, Wildermann S, Teich J Conference contribution, Conference Contribution History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs (2024) Esper K, Teich J Conference contribution, Conference Contribution Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems (2024) Letras M, Falk J, Teich J Journal article, Online publication SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation (2024) Plagwitz P, Hannig F, Teich J, Keszöcze O Conference contribution, Original article Accelerating DNNs using Weight Clustering on RISC-V Custom Functional Units (2024) Sabih M, Sesli B, Hannig F, Teich J Conference contribution, Conference Contribution Estimating the Execution Time of CNN Inference on GPUs (2024) Groth S, Schmid M, Teich J, Hannig F Conference contribution, Original article Compiler-based Processor Network Generation for Neural Networks on FPGAs (2024) Plagwitz P, Hannig F, Teich J, Keszöcze O Conference contribution, Original article Fused-Layer CNNs for Memory-Efficient Inference on Microcontrollers (2024) Deutel M, Hannig F, Mutschler C, Teich J Conference contribution, Conference Contribution Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs (2024) Sabih M, Karim A, Wittmann J, Hannig F, Teich J Conference contribution, Conference Contribution Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study (2024) Wilbert N, Wildermann S, Teich J Conference contribution, Conference Contribution