Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism (2008) Schaffer R, Merker R, Hannig F, Teich J Conference contribution Classification of general data flow actors into known models of computation (2008) Zebelein C, Falk J, Haubelt C, Teich J Conference contribution, Conference Contribution Entdecke die Möglichkeiten (2008) Dorsch R, Haubelt C, Teich J Journal article The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications (2008) Hannig F, Ruckdeschel H, Teich J Conference contribution Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices (2008) Dutta H, Hannig F, Ruckdeschel H, Teich J Conference contribution PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications (2008) Hannig F, Ruckdeschel H, Dutta H, Teich J Conference contribution Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures (2008) Wolinski C, Kuchcinski K, Teich J, Hannig F Conference contribution No-Break Dynamic Defragmentation of Reconfigurable Devices (2008) Fekete SP, Kamphans T, Schweer N, Tessars C, Van Der Veen JC, Angermeier J, Koch D, Teich J Conference contribution Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs (2008) Schmid M, Ziener D, Teich J Conference contribution Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads (2008) Angermeier J, Teich J Conference contribution