Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Dynamic task binding for hardware/software reconfigurable networks (2006) Streichert T, Strengert C, Haubelt C, Teich J Conference contribution, Conference Contribution Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology (2006) Dutta H, Hannig F, Teich J Journal article Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems (2006) Koch D, Streichert T, Teich J, Haubelt C Journal article Task-accurate performance modeling in SystemC for real-time multi-processor architectures (2006) Streubühr M, Falk J, Teich J, Haubelt C, Dorsch R, Schlipf T Conference contribution, Conference Contribution Minimizing communication cost for reconfigurable slot modules (2006) Fekete SP, Van Der Veen JC, Majer M, Teich J Conference contribution Controller Synthesis for Mapping Partitioned Programs on Array Architectures (2006) Dutta H, Hannig F, Teich J Conference contribution Topic 18: Embedded Parallel Systems (2006) Teich J, Kaxiras S, Plaks T, Flautner K Conference contribution Searching RC5-Keys with Distributed Reconfigurable Computing (2006) Koch D, Teich J, Körber M Conference contribution Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints (2006) Dutta H, Hannig F, Teich J Conference contribution Identifying FPGA IP-Cores based on Lookup Table Content Analysis (2006) Ziener D, Aßmus Stefan AS, Teich J Conference contribution