Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Modeling of Interconnection Networks in Massively Parallel Processor Architectures (2006) Kupriyanov O, Hannig F, Kissler D, Teich J, Lallet J, Sentieys O, Pillement S Other publication type Automatische Verification von ADeVA-Spezifikationen (2005) Dinkel T, Haubelt C, Heinkel U, Schlichter T, Teich J Conference contribution Evaluation of Watermarking methods for FPGA-based IP-cores (2005) Ziener D, Teich J Other publication type Online hardware/software partitioning in networked embedded systems (2005) Streichert T, Haubelt C, Teich J Conference contribution, Conference Contribution Distributed HW/SW-partitioning for embedded reconfigurable networks (2005) Streichert T, Haubelt C, Teich J Conference contribution, Conference Contribution SPI-Workbench – Modellierung, Analyse und Optimierung eingebetteter Systeme (2005) Haubelt C, Jersak M, Richter K, Strehl K, Ziegenbein D, Ernst R, Teich J, Thiele L Book chapter / Article in edited volumes Representing Models of Computation in SystemC (2005) Falk J, Haubelt C, Teich J Conference contribution Packet Routing in Dynamically Changing Networks on Chip (2005) Ahmadinia A, Bobda C, Majer M, Teich J Conference contribution Using symbolic feasibility tests during design space exploration of heterogeneous multi-processor systems (2005) Schlichter T, Hannig F, Haubelt C, Teich J Conference contribution, Conference Contribution Quad-trees: A Data structure for storing Pareto-sets in Multi-objective Evolutionary Algorithms with Elitism (2005) Mostaghim S, Teich J Book chapter / Article in edited volumes