Approximate synthesis for LUT count reduction via probabilistic error propagation
Schlögl T, Keszocze O (2025)
Publication Type: Journal article
Publication year: 2025
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Abstract
Approximate computing is an fast developing area for resource-efficient and fast designs that trades off computational accuracy with non-functional aspects such as delay, energy requirements or area. It can be used for applications where it is acceptable to compute inaccurate results such as image processing. A lot of work has been published on approximate synthesis for ASICs. As FPGAs are becoming more prevalent, approximation techniques for this technology should be developed. Lookup tables are a scarce resource on FPGAs. Consequently, we present and evaluate multiple approaches for reducing the number of lookup tables required to implement a given design on an FPGA. Our approaches work by removing either wires or entire lookup tables from a lookup table network. We can show that our approach is faster than related work while removing a comparable number of lookup tables (more in most cases).
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APA:
Schlögl, T., & Keszocze, O. (2025). Approximate synthesis for LUT count reduction via probabilistic error propagation. it - Information Technology. https://doi.org/10.1515/itit-2024-0074
MLA:
Schlögl, Thomas, and Oliver Keszocze. "Approximate synthesis for LUT count reduction via probabilistic error propagation." it - Information Technology (2025).
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