A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI
Nouripayam M, Rodrigues J, Luo X, Johansson T, Mohammadi B (2021)
Publication Type: Conference contribution
Publication year: 2021
Publisher: Institute of Electrical and Electronics Engineers Inc.
Pages Range: 459-462
Conference Proceedings Title: ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings
Event location: Virtual, Online, FRA
ISBN: 9781665437479
DOI: 10.1109/ESSCIRC53450.2021.9567785
Abstract
A 32 Kb dual-port low-voltage SRAM in 28 nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual-port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1MHz is measured at VMIN of 0.29 V. The highest energy efficiency of 1.35 fJ/bit-access is obtained at 80 MHz access rate, at a VDD of 0.54 V.
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APA:
Nouripayam, M., Rodrigues, J., Luo, X., Johansson, T., & Mohammadi, B. (2021). A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings (pp. 459-462). Virtual, Online, FRA: Institute of Electrical and Electronics Engineers Inc..
MLA:
Nouripayam, Masoud, et al. "A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI." Proceedings of the 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021, Virtual, Online, FRA Institute of Electrical and Electronics Engineers Inc., 2021. 459-462.
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