An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI

Mohammadi B, Andersson O, Luo X, Nouripayam M, Rodrigues JN (2017)

Publication Type: Conference contribution

Publication year: 2017

Publisher: Institute of Electrical and Electronics Engineers Inc.

Pages Range: 229-232

Conference Proceedings Title: 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings

Event location: Toyama, JPN

ISBN: 9781509037001

DOI: 10.1109/ASSCC.2016.7844177

Abstract

An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28 nm FD-SOI technology and different design parameters were verified by measurements. The results confirm an increased system-wise performance and power efficiency at a low area overhead of 2.7%. A performance of 37.5 MHz for a boost ratio of 2x, and an average energy dissipation of 41 fJ per operation, was observed at 0.36 V.

Involved external institutions

Lund University / Lunds universitet

Sweden (SE)

How to cite

APA:

Mohammadi, B., Andersson, O., Luo, X., Nouripayam, M., & Rodrigues, J.N. (2017). An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI. In 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings (pp. 229-232). Toyama, JPN: Institute of Electrical and Electronics Engineers Inc..

MLA:

Mohammadi, Babak, et al. "An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI." Proceedings of the 12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, JPN Institute of Electrical and Electronics Engineers Inc., 2017. 229-232.

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