A continuous-time delta-sigma ADC with integrated digital background calibration

Tan S, Miao Y, Palm M, Rodrigues JN, Andreani P (2016)

Publication Type: Journal article

Publication year: 2016

Journal

Analog Integrated Circuits and Signal Processing Springer Verlag (Germany)

Book Volume: 89

Pages Range: 273-282

Journal Issue: 2

DOI: 10.1007/s10470-016-0800-7

Abstract

This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

Involved external institutions

Lund University / Lunds universitet SE Sweden (SE) Ericsson SE Sweden (SE)

How to cite

APA:

Tan, S., Miao, Y., Palm, M., Rodrigues, J.N., & Andreani, P. (2016). A continuous-time delta-sigma ADC with integrated digital background calibration. Analog Integrated Circuits and Signal Processing, 89(2), 273-282. https://doi.org/10.1007/s10470-016-0800-7

MLA:

Tan, Siyu, et al. "A continuous-time delta-sigma ADC with integrated digital background calibration." Analog Integrated Circuits and Signal Processing 89.2 (2016): 273-282.

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