Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS

Andersson O, Mohammadi B, Meinerzhagen P, Burg A, Rodrigues JN (2013)

Publication Type: Conference contribution

Publication year: 2013

Pages Range: 197-200

Conference Proceedings Title: European Solid-State Circuits Conference

Event location: ROU

ISBN: 9781479906437

DOI: 10.1109/ESSCIRC.2013.6649106

Abstract

Two standard-cell based subthreshold (sub-VT) memories (SCMs) are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual-V T approach to improve reliability and balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implementation; and 2) a purely MUX-based implementation with the first stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65nm CMOS technology show that read access speed increases by 4X and 8X compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7X and 2X to 39 and 29 fJ, respectively. © 2013 IEEE.

Involved external institutions

Lund University / Lunds universitet SE Sweden (SE) École Polytechnique Fédérale de Lausanne (EPFL) CH Switzerland (CH)

How to cite

APA:

Andersson, O., Mohammadi, B., Meinerzhagen, P., Burg, A., & Rodrigues, J.N. (2013). Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. In European Solid-State Circuits Conference (pp. 197-200). ROU.

MLA:

Andersson, Oskar, et al. "Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS." Proceedings of the 39th European Solid-State Circuits Conference, ESSCIRC 2013, ROU 2013. 197-200.

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