Constantin J, Dogan A, Andersson O, Meinerzhagen P, Rodrigues J, Atienza D, Burg A (2013)
Publication Type: Conference contribution
Publication year: 2013
Publisher: Springer New York LLC
Book Volume: 418
Pages Range: 88-106
Conference Proceedings Title: IFIP Advances in Information and Communication Technology
Event location: USA
ISBN: 9783642450723
DOI: 10.1007/978-3-642-45073-0_5
Compressed sensing (CS) is a universal low-complexity data compression technique for signals that have a sparse representation in some domain. While CS data compression can be done both in the analog- and digital domain, digital implementations are often used on low-power sensor nodes, where an ultra-low-power (ULP) processor carries out the algorithm on Nyquist-rate sampled data. In such systems an energy-efficient implementation of the CS compression kernel is a vital ingredient to maximize battery lifetime. In this paper, we propose an application-specific instruction-set processor (ASIP) processor that has been optimized for CS data compression and for operation in the subthreshold (sub-V
APA:
Constantin, J., Dogan, A., Andersson, O., Meinerzhagen, P., Rodrigues, J., Atienza, D., & Burg, A. (2013). An ultra-low-power application-specific processor with sub-VT memories for compressed sensing. In Matthew R. Guthaus, Srinivas Katkoori, Ayse Coskun, Andreas Burg, Srinivas Katkoori, Ricardo Reis, Ricardo Reis, Andreas Burg, Ayse Coskun, Matthew Guthaus (Eds.), IFIP Advances in Information and Communication Technology (pp. 88-106). USA: Springer New York LLC.
MLA:
Constantin, Jeremy, et al. "An ultra-low-power application-specific processor with sub-VT memories for compressed sensing." Proceedings of the 20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, USA Ed. Matthew R. Guthaus, Srinivas Katkoori, Ayse Coskun, Andreas Burg, Srinivas Katkoori, Ricardo Reis, Ricardo Reis, Andreas Burg, Ayse Coskun, Matthew Guthaus, Springer New York LLC, 2013. 88-106.
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