A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS

Meinerzhagen P, Andersson O, Mohammadi B, Sherazi Y, Burg A, Rodrigues JN (2012)

Publication Type: Conference contribution

Publication year: 2012

Pages Range: 321-324

Conference Proceedings Title: European Solid-State Circuits Conference

Event location: FRA

ISBN: 9781467322126

DOI: 10.1109/ESSCIRC.2012.6341319

Abstract

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub-VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D-latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220 mV) and a total energy of 14 fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65nm CMOS reported to date. © 2012 IEEE.

Involved external institutions

École Polytechnique Fédérale de Lausanne (EPFL)

Switzerland (CH) Lund University / Lunds universitet

Sweden (SE)

How to cite

APA:

Meinerzhagen, P., Andersson, O., Mohammadi, B., Sherazi, Y., Burg, A., & Rodrigues, J.N. (2012). A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. In European Solid-State Circuits Conference (pp. 321-324). FRA.

MLA:

Meinerzhagen, Pascal, et al. "A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS." Proceedings of the 38th European Solid State Circuits Conference, ESSCIRC 2012, FRA 2012. 321-324.

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