Impact of switching activity on the energy minimum voltage for 65 nm sub-V T CMOS

Andersson O, Sherazi SM, Rodrigues JN (2011)

Publication Type: Conference contribution

Publication year: 2011

Conference Proceedings Title: 2011 NORCHIP

Event location: SWE

ISBN: 9781457705168

DOI: 10.1109/NORCHP.2011.6126748

Abstract

This paper presents an analysis on energy dissipation of designs when operated in sub-threshold (sub-V T) regime. Four reference architectures are used to investigate the impact of switching activity μ e on energy and energy minimum voltage (EMV). The designs are synthesized in a 65 nm low-leakage CMOS technology with high-threshold voltages cells. A sub-V T energy model is applied to characterize the designs in the sub-V T domain. The simulation results show that with low μ e the EMV of a design moves closer to the threshold voltage and visa versa, up to a change of 104mV for the observed architectures. Furthermore a loss in frequency by one order of magnitude is observed. It is also observed that for these architectures operation at a sub-optimal frequency leads to loss in energy dissipation. However, by correct selection of operational clock frequency the energy dissipation is reduced by order of magnitudes. © 2011 IEEE.

Involved external institutions

Lund University / Lunds universitet

Sweden (SE)

How to cite

APA:

Andersson, O., Sherazi, S.M., & Rodrigues, J.N. (2011). Impact of switching activity on the energy minimum voltage for 65 nm sub-V T CMOS. In 2011 NORCHIP. SWE.

MLA:

Andersson, Oskar, S. M.Yasser Sherazi, and Joachim Neves Rodrigues. "Impact of switching activity on the energy minimum voltage for 65 nm sub-V T CMOS." Proceedings of the 2011 NORCHIP, SWE 2011.

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