A GALS ASIC implementation from a CAL dataflow description
Prabhu H, Thomas S, Rodrigues J, Olsson T, Carlsson A (2011)
Publication Type: Conference contribution
Publication year: 2011
Conference Proceedings Title: 2011 NORCHIP
Event location: SWE
ISBN: 9781457705168
DOI: 10.1109/NORCHP.2011.6126740
Abstract
This paper presents low power hardware generation, based on a CAL actor language dataflow implementation. The CAL language gives a higher level of abstraction and generate both hardware and software description. The original CAL flow is targeted for hardware-software co-design of complex systems on FPGA. Modifications are done to the original CAL flow to facilitate low power ASIC implementations. The hardware-software co-design and Globally Asynchronous Locally Synchronous (GALS) design at a higher level of abstraction provides more freedom for design-space exploration and reduced design time. Performance is evaluated by a reference design, Orthogonal Frequency-Division Multiplexing (OFDM) multi-standard channel estimator based on robust Minimum Mean-Square Error (MMSE) algorithm. Higher throughput is attained due to inherent parallelism in CAL dataflow and reduced design time for GALS implementation. © 2011 IEEE.
Involved external institutions
Sweden (SE)How to cite
APA:
Prabhu, H., Thomas, S., Rodrigues, J., Olsson, T., & Carlsson, A. (2011). A GALS ASIC implementation from a CAL dataflow description. In 2011 NORCHIP. SWE.
MLA:
Prabhu, Hemanth, et al. "A GALS ASIC implementation from a CAL dataflow description." Proceedings of the 2011 NORCHIP, SWE 2011.
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