A <1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS
Rodrigues JN, Akgun OC, Öwall V (2010)
Publication Type: Conference contribution
Publication year: 2010
Pages Range: 253-258
Conference Proceedings Title: Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
Event location: ESP
ISBN: 9781424464708
DOI: 10.1109/VLSISOC.2010.5642669
Abstract
This paper presents the hardware implementation of a wavelet based event detector for cardiac pacemakers. A high level energy estimation flow was applied to evaluate energy efficiency of standard-cell based designs, over several CMOS technology generations, from 180 to 65 nm, operated in the sub-threshold domain. The simulation results indicate a 65 nm low-leakage high-threshold (LL-HVT) CMOS technology as the favourable choice. Accordingly, the design was fabricated in 65nm LL-HVT CMOS. Measurements validate the simulation results and prove that the circuit is fully functional down to a supply voltage of 250mV. At the energy minimum voltage of 320mV the circuit dissipates 0.88 pJ per sample at a clock rate of 20 kHz. ©2010 IEEE.
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Sweden (SE)How to cite
APA:
Rodrigues, J.N., Akgun, O.C., & Öwall, V. (2010). A <1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS. In Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 (pp. 253-258). ESP.
MLA:
Rodrigues, Joachim Neves, Omer Can Akgun, and Viktor Öwall. "A <1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS." Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010, ESP 2010. 253-258.
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