Ultra low energy vs throughput design exploration of 65 nm sub-V T CMOS digital filters

Sherazi SM, Rodrigues JN, Akgun OC, Sjöland H, Nilsson P (2010)

Publication Type: Conference contribution

Publication year: 2010

Conference Proceedings Title: 28th Norchip Conference, NORCHIP 2010

Event location: FIN

ISBN: 9781424489732

DOI: 10.1109/NORCHIP.2010.5669452

Abstract

This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4 architecture, however, is the best for throughput requirements of around 120 Ksamples/sec to 1 Msamples/s, as it dissipates less energy than any other implementation in this speed range. ©2010 IEEE.

Involved external institutions

Lund University / Lunds universitet SE Sweden (SE)

How to cite

APA:

Sherazi, S.M., Rodrigues, J.N., Akgun, O.C., Sjöland, H., & Nilsson, P. (2010). Ultra low energy vs throughput design exploration of 65 nm sub-V T CMOS digital filters. In 28th Norchip Conference, NORCHIP 2010. FIN.

MLA:

Sherazi, S. M.Yasser, et al. "Ultra low energy vs throughput design exploration of 65 nm sub-V T CMOS digital filters." Proceedings of the 28th Norchip Conference, NORCHIP 2010, FIN 2010.

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