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Energy dissipation reduction of a cardiac event detector in the sub-V t domain by architectural folding

Rodrigues JN, Akgun OC, Acharya P, De La Calle A, Leblebici Y, Öwall V (2010)

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Publication Type: Conference contribution

Publication year: 2010

Journal

Book Volume: 5953 LNCS

Pages Range: 347-356

Conference Proceedings Title: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Event location: NLD

ISBN: 3642118011

DOI: 10.1007/978-3-642-11802-9_39

Abstract

This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency in the sub-threshold (sub-V T ) domain. The design is synthesized in 65 nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Folding decreases energy dissipation of the circuit by 14.4 % in the sub-V T regime, where the circuit dissipates 3.3 pJ per sample at V DD =0.26 V. © 2010 Springer Berlin Heidelberg.

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How to cite

APA:

Rodrigues, J.N., Akgun, O.C., Acharya, P., De La Calle, A., Leblebici, Y., & Öwall, V. (2010). Energy dissipation reduction of a cardiac event detector in the sub-V t domain by architectural folding. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (pp. 347-356). NLD.

MLA:

Rodrigues, Joachim Neves, et al. "Energy dissipation reduction of a cardiac event detector in the sub-V t domain by architectural folding." Proceedings of the 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, NLD 2010. 347-356.

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