Hardware implementation of an iterative sampling rate converter for wireless communication
Stala M, Bilgin C, Gangarajaiah R, Rodrigues JN (2010)
Publication Type: Conference contribution
Publication year: 2010
Publisher: Institute of Electrical and Electronics Engineers Inc.
Conference Proceedings Title: GLOBECOM - IEEE Global Telecommunications Conference
Event location: Miami, FL, USA
ISBN: 9781424456383
DOI: 10.1109/GLOCOM.2010.5683286
Abstract
This paper presents a new technique for fractional sample rate conversion based on an iterative Sinc (ISRC) method. The proposed algorithm was evaluated against the Farrow resampler, and performance simulation targeting different signal-to-noise ratios show the ISRC qualifies for application in reconfigurable terminals. The architecture was implemented in 65nm CMOS technology, and synthesis results show that the ISRC requires at least 23% less silicon area, compared to a Farrow filter with similar performance. The generic nature of the architecture enables further area reduction by time-multiplexing. ©2010 IEEE.
Involved external institutions
Switzerland (CH)
Sweden (SE)How to cite
APA:
Stala, M., Bilgin, C., Gangarajaiah, R., & Rodrigues, J.N. (2010). Hardware implementation of an iterative sampling rate converter for wireless communication. In GLOBECOM - IEEE Global Telecommunications Conference. Miami, FL, USA: Institute of Electrical and Electronics Engineers Inc..
MLA:
Stala, Michal, et al. "Hardware implementation of an iterative sampling rate converter for wireless communication." Proceedings of the 53rd IEEE Global Communications Conference, GLOBECOM 2010, Miami, FL, USA Institute of Electrical and Electronics Engineers Inc., 2010.
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