Low-overhead Bitwise Shifting in DRAM

Tegge WC, Cardoso De Lima JP, Morris BF, Jones AK (2026)

Publication Type: Conference contribution

Publication year: 2026

Publisher: Association for Computing Machinery, Inc

Pages Range: 715-716

Conference Proceedings Title: GLSVLSI 2026 - Proceedings of the Great Lakes Symposium on VLSI 2026

Event location: Canandaigua, NY, USA

ISBN: 9798400724312

DOI: 10.1145/3787109.3815319

Abstract

Processing-in-Memory (PIM) architectures enable computation directly within DRAM and help combat the memory wall problem. While commodity DRAM has been demonstrated for data movement and bulk-bitwise PIM, data must be reorganized away from row-wise ordering and byte addressability used by typical processors into a column-ordering where bytes and words are spread across rows within a single column since there is no mechanism to move data between bitlines which is required for many computational operations including addition and multiplication. In this paper, we propose a DRAM subarray design that enables in-DRAM bit-shifting for open-bitline architectures. By adding migration cells at the top and bottom of each subarray, bidirectional bit-shifting may be conducted within any given row. In this paper we present initial findings and evaluation of potential timing and energy analysis using a combination of approaches from VLSI layout, spice simulation and demonstrate integration into NVMain-PIM a simulator extended with DRAM PIM primitives.

Involved external institutions

Syracuse University US United States (USA) (US) Technische Universität Dresden DE Germany (DE) Duke University US United States (USA) (US)

How to cite

APA:

Tegge, W.C., Cardoso De Lima, J.P., Morris, B.F., & Jones, A.K. (2026). Low-overhead Bitwise Shifting in DRAM. In Fan Chen, Peipei Zhou, Jie Gu, Amit R. Trivedi, Xiaoxuan Yang (Eds.), GLSVLSI 2026 - Proceedings of the Great Lakes Symposium on VLSI 2026 (pp. 715-716). Canandaigua, NY, USA: Association for Computing Machinery, Inc.

MLA:

Tegge, William C., et al. "Low-overhead Bitwise Shifting in DRAM." Proceedings of the 36th Great Lakes Symposium on VLSI, GLSVLSI 2026, Canandaigua, NY, USA Ed. Fan Chen, Peipei Zhou, Jie Gu, Amit R. Trivedi, Xiaoxuan Yang, Association for Computing Machinery, Inc, 2026. 715-716.

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