Count2Multiply: Reliable In-Memory High-Radix Counting

De Lima JPC, Morris B, Khan AA, Castrillon J, Jones AK (2026)


Publication Type: Conference contribution

Publication year: 2026

Journal

Publisher: IEEE Computer Society

Conference Proceedings Title: Proceedings - International Symposium on High-Performance Computer Architecture

Event location: Sydney, AUS

ISBN: 9798331593025

DOI: 10.1109/HPCA68181.2026.11408436

Abstract

Computing-in-memory (CIM) has been demonstrated across various memory technologies, from memristive crossbars for analog dot-products to large-scale digital bitwise operations in commodity DRAM and other non-volatile memory technologies. However, current CIM solutions face challenges related to latency and reliability. CIM fidelity lags considerably behind standard memory access fidelity. Furthermore, bulkbitwise CIM, though highly parallel, requires long latency for multiplication and addition due to bit-serial execution. This paper presents Count2Multiply, a digital CIM framework that performs multiplication, addition, and other operations using high-radix, massively parallel counting enabled by bulk-bitwise inmemory operations. Designed to meet fault tolerance requirements, Count2Multiply integrates traditional row-wise error correction codes, such as Hamming and BCH, to address the high error rates in existing CIM designs. We demonstrate Count2Multiply in commodity DRAMs, achieving on average 1.5× speedup, 4.6× higher energy efficiency (GOPS/Watt), and 4.4× better area efficiency (GOPS/mm2) over NVIDIA A100; and 9.7×, 8.1×, and 12.9× improvements, respectively, over SIMDRAM.

Involved external institutions

How to cite

APA:

De Lima, J.P.C., Morris, B., Khan, A.A., Castrillon, J., & Jones, A.K. (2026). Count2Multiply: Reliable In-Memory High-Radix Counting. In Proceedings - International Symposium on High-Performance Computer Architecture. Sydney, AUS: IEEE Computer Society.

MLA:

De Lima, Joao Paulo C., et al. "Count2Multiply: Reliable In-Memory High-Radix Counting." Proceedings of the 32nd IEEE International Symposium on High-Performance Computer Architecture, HPCA 2026, Sydney, AUS IEEE Computer Society, 2026.

BibTeX: Download