Muhammad Sabih

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow (2025) Sesli B, Sabih M, Hannig F, Teich J Conference contribution, Conference Contribution Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks using RISC-V Custom Functional Units (2025) Sabih M, Abdo M, Hannig F, Teich J Conference contribution, Conference Contribution Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks (2024) Heidorn C, Sabih M, Meyerhöfer N, Schinabeck C, Teich J, Hannig F Journal article Accelerating DNNs using Weight Clustering on RISC-V Custom Functional Units (2024) Sabih M, Sesli B, Hannig F, Teich J Conference contribution, Conference Contribution Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs (2024) Sabih M, Karim A, Wittmann J, Hannig F, Teich J Conference contribution, Conference Contribution Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods (2023) Sabih M, Yayla M, Hannig F, Teich J, Chen JJ Conference contribution, Conference Contribution MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks (2022) Mishra A, Hannig F, Teich J, Sabih M Conference contribution, Conference Contribution DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks (2022) Sabih M, Hannig F, Teich J Conference contribution, Conference Contribution Fault-Tolerant Low-Precision DNNs using Explainable AI (2021) Sabih M, Hannig F, Teich J Conference contribution, Conference Contribution Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks (2020) Sabih M, Hannig F, Teich J Other publication type