Co-Design of Massively Parallel Embedded Processor Architectures (CoMap)

Third party funded individual grant

Acronym: CoMap

Start date : 01.01.2005

End date : 31.12.2011

Website: https://www.cs12.tf.fau.de/forschung/projekte/comap

Overview

Publications

(47)

Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays (2011) Kissler D, Hannig F, Teich J Journal article Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays (2011) Kissler D, Gran D, Salcic Z, Hannig F, Teich J Journal article Compilation Techniques for CGRAs: Exploring All Parallelization Approaches (2010) Vander Aa T, Raghavan P, Mahlke S, De Sutter B, Shrivastava A, Hannig F Conference contribution Modeling and synthesis of communication subsystems for loop accelerator pipelines (2010) Dutta H, Hannig F, Schmid M, Keinert J Conference contribution, Conference Contribution Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures (2009) Kissler D, Strawetz A, Hannig F, Teich J Journal article A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors (2009) Dutta H, Kissler D, Hannig F, Kupriyanov O, Teich J, Pottier B Journal article Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis (2009) Dutta H, Hannig F, Teich J Conference contribution Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines (2009) Dutta H, Zhai J, Hannig F, Teich J Conference contribution Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning (2009) Hannig F, Dutta H, Teich J Conference contribution Model-based synthesis and optimization of static multi-rate image processing algorithms (2009) Keinert J, Dutta H, Hannig F, Haubelt C, Teich J Conference contribution, Conference Contribution

‹ 1 2 3 ... 5 ›